View MPC9448_462257.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
Freescale SEMICONDUCTOR TECHNICAL DATA Semiconductor, Inc.
Order Number: MPC9448/D Rev 3, 04/2003
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications.
MPC9448
Freescale Semiconductor, Inc...
* * * * * * * * * * *
12 LVCMOS compatible clock outputs Selectable LVCMOS and differential LVPECL compatible clock inputs Maximum clock frequency of 350 MHz Maximum clock skew of 150 ps Synchronous output stop in logic low state eliminates output runt pulses High--impedance output control 3.3V or 2.5V power supply Drives up to 24 series terminated clock lines Ambient temperature range --40C to +85C 32--Lead LQFP packaging
LOW VOLTAGE 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER
Supports clock distribution in networking, telecommunication and computing applications * Pin and function compatible to MPC948
FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A
Functional Description The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50 terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into high--impedance mode. All inputs have an internal pull--up or pull--down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of --40C to +85C. The MPC9448 is pin and function compatible but performance--enhanced to the MPC948.
(c) Motorola, Inc. 2003
For More Information On This Product, Go to: www.freescale.com
1
MPC9448
Freescale Semiconductor, Inc.
Q0 GND GND VCC VCC 18 Q1 0 1 CLK STOP Q2 24 Q3 VCC Q4 Q5 VCC Q6 SYNC Q7 Q8 Q9 Q10 VCC Q11 Q3 VCC Q2 GND Q1 VCC Q0 GND 25 26 27 28 29 30 31 32 1 CLK_SEL 2 CCLK 3 PCLK 4 PCLK 5 CLK_STOP 6 OE 7 VCC 8 GND 23 22 21 20 19 17 16 15 14 GND Q8 VCC Q9 GND Q10 VCC Q11
VCC PCLK PCLK CCLK
Q4
Q5
Q6
CLK_SEL
MPC9448
CLK_STOP
Freescale Semiconductor, Inc...
Q7 13 12 11 10 9
OE
(all input resistors have a value of 25k)
Figure 1. Logic Diagram
Figure 2. 32-Lead Package Pinout (Top View)
Table 1. FUNCTION TABLE
Control CLK_SEL OE CLK_STOP Default 1 1 1 0 PECL differential input selected Outputs disabled (high-impedance state)1 Outputs synchronously stopped in logic low state CCLK input selected Outputs enabled Outputs active 1
1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.
Table 2. PIN CONFIGURATION
Pin PCLK, PCLK CCLK CLK_SEL CLK_STOP OE Q0--11 GND VCC I/O Input Input Input Input Input Output Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Clock signal input Alternative clock signal input Clock input select Clock output enable/disable Output enable/disable (high--impedance tristate) Clock outputs Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
MOTOROLA
For More Information On This Product, Go to: www.freescale.com
2
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
Table 3. ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT TStor Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Range --65 Parameter Min --0.3 --0.3 --0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125
MPC9448
Unit V V V mA mA C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied.
Table 4. GENERAL SPECIFICATIONS
Freescale Semiconductor, Inc...
Symbol VTT MM HBM LU CPD CIN
Characteristic Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch--up Immunity Power Dissipation Capacitance Input Capacitance
Min
Typ VCC 2
Max
Unit V V V mA
Condition
200 2000 200 10 4.0
pF pF
Per Output Inputs
Table 5. DC CHARACTERISTICS (VCC = 3.3V 5%, TA = --40C to +85C)
Symbol VIH VIL VPP VCMR IIN VOH VOL ZOUT ICCQ
d a
Characteristic Input HIGH Voltage Input LOW Voltage Peak--to--Peak Input Voltage Common Mode Range Input Currentb PCLK PCLK
Min 2.0 --0.3 250 1.1
Typ
Max VCC + 0.3 0.8
Unit V V mV
Condition LVCMOS LVCMOS LVPECL LVPECL VIN = VCC or GND IOH = --24mAc IOL = 24mAc IOL = 12mA
VCC -- 0.6 300
V A V
Output HIGH Voltage Output LOW Voltage Output Impedance Maximum Quiescent Supply Current
2.4 0.55 0.30 17 2.0
V V mA
All VCC Pins
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. Input pull-up / pull-down resistors influence input current. c. The MPC9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC=3.3V) or one 50 series terminated transmission line (for VCC=2.5V). d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
TIMING SOLUTIONS
For More Information On This Product, Go to: www.freescale.com
3
MOTOROLA
MPC9448
Freescale Semiconductor, Inc.
Table 6. AC CHARACTERISTICS (VCC = 3.3V 5%, TA = --40C to +85C)a
Symbol fref fMAX VPP VCMRb tP, REF tr, tf tPLH/HL tPLH/HL tPLZ, HZ tPZL, LZ tS Input Frequency Maximum Output Frequency Peak-to-peak input voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time Setup time Hold time Output-to-output Skew Device-to-device Skew Output pulse skewd Output Duty Cycle Output Rise/Fall Time PCLK or CCLK to any Q Using CCLK Using PCLK fQ<170 MHz 45 0.1 50 CCLK to CLK_STOP PCLK to CLK_STOP CCLK to CLK_STOP PCLK to CLK_STOP 0.0 0.0 1.0 1.5 150 2.0 300 400 55 1.0 PCLK to any Q CCLK to any Q 1.6 1.3 PCLK PCLK Characteristics Min 0 0 400 1.3 1.4 1.0c 3.6 3.3 11 11 Typ Max 350 350 1000 VCC-0.8 Unit MHz MHz mV V ns ns ns ns ns ns ns ns ns ns ps ns ps ps % ns DCREF = 50% 0.55 to 2.4V 0.8 to 2.0V LVPECL LVPECL Condition
Freescale Semiconductor, Inc...
tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf
a. AC characteristics apply for parallel output termination of 50 to VTT. b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). c. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. d. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 7. DC CHARACTERISTICS (VCC = 2.5V 5%, TA = --40C to +85C)
Symbol VIH VIL VPP VCMR IIN VOH VOL ZOUT ICCQd
a
Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Input currentb Output High Voltage Output Low Voltage Output impedance Maximum Quiescent Supply Current PCLK PCLK
Min 1.7 -0.3 250 1.0 1.8
Typ
Max VCC + 0.3 0.7 VCC-0.7 300 0.6
Unit V V mV V A V V mA
Condition LVCMOS LVCMOS LVPECL LVPECL VIN=GND or VIN=VCC IOH= -15 mAc IOL= 15 mAc All VCC Pins
19 2.0
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. Input pull-up / pull-down resistors influence input current. c. The MPC9448 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission lines at VCC=2.5V. d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
MOTOROLA
For More Information On This Product, Go to: www.freescale.com
4
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
Table 8. AC CHARACTERISTICS (VCC = 2.5V 5%, TA = --40C to +85C)a
Symbol fref fMAX VPP VCMR tr, tf tPLH/HL tPLH/HL tPLZ, HZ tPZL, LZ tS
b
MPC9448
Characteristics Input Frequency Maximum Output Frequency Peak-to-peak input voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay Output Disable Time Output Enable Time Setup time Hold time Output-to-output Skew Device-to-device Skew Output pulse skewd Output Duty Cycle Output Rise/Fall Time PCLK or CCLK to any Q Using CCLK Using PCLK fQ< 350 MHz and using CCLK fQ<200 MHz and using PCLK CCLK to CLK_STOP PCLK to CLK_STOP CCLK to CLK_STOP PCLK to CLK_STOP PCLK to any Q CCLK to any Q PCLK PCLK
Min 0 0 400 1.2 1.4
Typ
Max 350 350 1000 VCC-0.8 1.0c
Unit MHz MHz mV V ns ns ns ns ns ns ns ns ns ns
Condition
LVPECL LVPECL 0.8 to 2.0V
tP, REF
1.5 1.7
4.2 4.4 11 11
0.0 0.0 1.0 1.5 150 2.7 200 300 45 45 0.1 50 50 55 55 1.0
Freescale Semiconductor, Inc...
tH tsk(O) tsk(PP) tSK(p) DCQ tr, tf
ps ns ps ps % % ns DCREF = 50% 0.6 to 1.8V
a. AC characteristics apply for parallel output termination of 50 to VTT. b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). c. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. d. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
TIMING SOLUTIONS
For More Information On This Product, Go to: www.freescale.com
5
MOTOROLA
MPC9448
Freescale Semiconductor, Inc.
APPLICATIONS INFORMATION
Figure 3. Output Clock Stop (CLK_STOP) Timing Diagram
CCLK or PCLK CLK_STOP VOLTAGE (V) Q0 to Q11
3.0 2.5 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (nS) 10 12 14 OutA tD = 3.8956 OutB tD = 3.9386
Freescale Semiconductor, Inc...
Driving Transmission Lines The MPC9448 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17 (VCC=3.3V), the outputs can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Motorola application note AN1091. In most high performance clock networks, point--to--point distribution of signals is the method of choice. In a point--to--point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2.
MPC9448 OUTPUT BUFFER IN
17
Figure 5. Single versus Dual Line Termination Waveforms
RS = 33
ZO = 50 OutA
MPC9448 OUTPUT BUFFER IN
17
RS = 33
ZO = 50 OutB0 ZO = 50 OutB1
RS = 33
The waveform plots in Figure 5 "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9448 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output--to--output skew of the MPC9448. The output waveform in Figure 5 "Single versus Dual Line Termination Waveforms" shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL Z0 RS R0 VL = VS ( Z0 / (RS+R0 +Z0)) = 50 || 50 = 33 || 33 = 17 = 3.0 ( 25 / (16.5+17+25) = 1.28V
Figure 4. Single versus Dual Transmission Lines This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9448 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 4 "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9448 clock driver is effectively doubled due to its capability to drive multiple lines at VCC=3.3V.
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
MOTOROLA
For More Information On This Product, Go to: www.freescale.com
6
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 6 "Optimized Dual Line Termination" should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9448
Table 9. Die junction temperature and MTBF
Junction temperature (C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0
MPC9448 OUTPUT BUFFER
17
RS = 16
ZO = 50
Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC9448 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC9448 is represented in equation 1. Where ICCQ is the static current consumption of the MPC9448, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the MPC9448). The MPC9448 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cyle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC9448 in a series terminated transmission line system, equation 4.
RS = 16
ZO = 50
Freescale Semiconductor, Inc...
17 + 16 k 16 = 50 k 50 25 = 25 Figure 6. Optimized Dual Line Termination
Power Consumption of the MPC9448 and Thermal Management The MPC9448 AC specification is guaranteed for the entire operating frequency range up to 350 MHz. The MPC9448 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperture, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC9448 die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability please refer to the application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature:
P TOT =
I
CCQ
+ V CC f CLOCK
NC
L
PD
+
C
M
L
V
CC
Equation 1
P TOT = V CC
I
CCQ
+ V CC f CLOCK
NC
PD
+
C
M
+
P
DC Q I OH V CC - V OH + 1 - DC Q I OL V OL Equation 2
T J = T A + P TOT R thja T J,MAX - T A 1 - I CCQ V CC R thja C PD N V 2 CC
Equation 3
f CLOCK,MAX =
Equation 4
TIMING SOLUTIONS
For More Information On This Product, Go to: www.freescale.com
7
MOTOROLA
MPC9448
Freescale Semiconductor, Inc.
If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the MPC9448. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made.
TJ,MAX should be selected according to the MTBF system requirements and Table 9. Rthja can be derived from Table 10. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. Table 10. Thermal package impedance of the 32LQFP
Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), C/W 86 76 71 68 66 60 Rthja (2P2S board), C/W 61 56 54 53 52 49
Freescale Semiconductor, Inc...
Figure 7. Maximum MPC9448 frequency, VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines, 2s2p board
Figure 8. Maximum MPC9448 frequency, VCC = 3.3V, MTBF 9.1 years, 4 pF load per line, 2s2p board
Figure 9. No maximum frequency limitation for VCC = 3.3V, MTBF 4 years, driving series terminated transmission lines, 2s2p board
Figure 10. Maximum MPC9448 frequency, VCC = 3.3V, MTBF 4 years, 4 pF load per line, 2s2p board
MOTOROLA
For More Information On This Product, Go to: www.freescale.com
8
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9448
The Following Figures Illustrate the Measurement Reference for the MPC9448 Clock Driver Circuit
MPC9448 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 11. CCLK MPC9448 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V
Freescale Semiconductor, Inc...
Differential Pulse Generator Z = 50
ZO = 50
MPC9448 DUT ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 12. PCLK MPC9448 AC Test Reference
TIMING SOLUTIONS
For More Information On This Product, Go to: www.freescale.com
9
MOTOROLA
MPC9448
PCLK PCLK VPP
Freescale Semiconductor, Inc.
CCLK VCC VCC/2 GND VCC VCC/2 GND tP(LH) tP(HL) tP(LH) tP(HL) QX VCC VCC/2 GND
VCMR
QX
Figure 13. Propagation Delay (tPD) Test Reference
Figure 14. Propagation Delay (tPD) Test Reference
VCC VCC/2 GND VCC CCLK VCC/2 GND QX tP(LH) tP(HL) tSK(P) = | tPLH -- tPHL | VCC VCC/2 GND
Freescale Semiconductor, Inc...
VCC VCC/2 GND tSK(LH) tSK(HL)
The pin--to--pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
Figure 15. Output- -Output Skew tSK(LH, HL) -to-
Figure 16. Output Pulse Skew (tSK(P)) Test Reference
VCC VCC/2 GND tP T0 DC = (tP T0 x 100%) The time from the output controlled edge to the non--controlled edge, divided by the time between output controlled edges, expressed as a percentage tF tR VCC=3.3V 2.4 0.55 VCC=2.5V 1.8V 0.6V
Figure 17. Output Duty Cycle (DC)
Figure 18. Output Transition Time Test Reference
VCC CCLK PCLK TJIT(CC) = |TN - TN+1 | VCC/2 GND VCC VCC/2 GND tS tH
TN
TN+1
CLK_STOP
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
Figure 19. Cycle- -Cycle Jitter -to-
Figure 20. Setup and Hold Time (tS, tH) Test Reference
MOTOROLA
For More Information On This Product, Go to: www.freescale.com
10
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A--03 ISSUE B
4X
MPC9448
D1
PIN 1 INDEX
6
0.20 H A--B D e/2
25
D1/2
32
3
A, B, D
1
E1/2 A 6 E1
B E
DETAIL G 8 17
F 4 F E/2 DETAIL G
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08--mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07--mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25--mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1--mm AND 0.25--mm FROM THE LEAD TIP.
Freescale Semiconductor, Inc...
7
9
D D 4
D/2
4X
0.20 C A--B D
H
SEATING PLANE
28X
e
32X
0.1 C
C
DETAIL AD
PLATING BASE METAL
b1 c b R R2 R R1 A A2 0.25
GAUGE PLANE
c1 5 8
DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 1 R1 R2 S
8X
( 1_)
0.20
M
C A--B D
SECTION F-F
A1
(S) (L1) DETAIL AD
L
_
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0_ 7_ 12 _REF 0.08 0.20 0.08 -----0.20 REF
TIMING SOLUTIONS
For More Information On This Product, Go to: www.freescale.com
11
MOTOROLA
MPC9448
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. E Motorola Inc. 2003 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: TECHNICAL INFORMATION CENTER: 1--800--521--6274 or 480--768--2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3--20--1, Minami--Azabu, Minato--ku, Tokyo 106--8573 Japan 81--3--3440--3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852--26668334 HOME PAGE: http://motorola.com/semiconductors
MOTOROLA
12 For More Information On This Product, Go to: www.freescale.com
MPC9448/D TIMING SOLUTIONS

▲Up To Search▲

Price & Availability of MPC9448

	To Download MPC9448 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .